The production of large scale integrated circuit semiconductor devices by the formation of patterned photoresist, interchangeably referred to herein as a resist, barrier layers on semiconductor wafers, interchangeably referred to herein as substrates, requires that such photoresist layers be sufficiently precise in shape and location to allow the reliable manufacture of extremely small structural configurations, and further that such layers be free of spurious hole defects. It is commonly known that the presence of such "pinhole" defects can when masking dielectric layers expose such layers to unwanted etching therethrough, and consequential short circuit paths following metallization. Because a defect in a single conductive path or device can cause a complete integrated circuit chip, consisting of thousands of such devices, to be inoperative, the elimination of such flaws has given rise to a variety of techniques aimed at holding their occurrence to an absolute minimum. Subsequent discussions will be concerned mainly with the use of such barrier layers as etching barriers; however, the limitations of the prior art and the advantages of the present invention thereover are equally applicable with respect to the common practice of using such patterns as selective masks for deposition, ion implantation, diffusion, lift-off, etc. operations.
Positive photoresists, those presently preferred for semiconductor processing, are usually formed from a polymer dissolved in an appropriate carrier solvent to create a lacquer, which lacquer is applied by conventional spin-on techniques to form a thin solid layer over a substrate after the carrier solvent is removed by evaporation. A subsequent selective exposure of the resist layer to depolymerizing wavelength radiation passed through a patterned mask, or alternatively by means of a direct projection of such actinic radiation, causes local depolymerization of the irradiated resist to the form of a monomer. Subsequent immersion of the resist coated substrate into a developer solvent having the ability to dissolve the resulting monomer, while having no substantial attack rate on the unexposed polymer, causes a retention of the desired polymer photoresist pattern. Alternatively, the selectively exposed layer may be "dry developed" by exposure to ionic plasmas of certain gases having similar selective dissolving characteristics.
For maximum resolution, i.e. to produce the smallest apertures in the resist, the thickness of the resist layer must be held to values of 500 nanometers or less. Unfortunately, resist barriers this thin very frequently exhibit flaws, in the nature of random pinhole defects. Such flaws arise from a variety of sources, including dust particles in the photolithographic system and mask defects. To prevent such pinholes in the resist barrier from giving rise to spurious etching patterns, a technique commonly employed in the prior art (see FIGS. 2A-2D) is to apply a second substantially thicker resist layer, initially in liquid form as before and frequently of the same composition as the first resist layer, over the first layer, after the first layer has been developed and suitably processed (hardened). The hardening ensures that the first layer is separated by an insoluble barrier from the carrier solvents in the second layer. The hardening process will be discussed subsequently. However, it should be recognized that without such a hardening process the carrier solvents of the second resist layer would immediately attack the patterned first layer of resist when the second layer is applied.
This second photoresist layer is typically applied to have a thickness in the range of 1000 to 2000 nanometers, a thickness sufficient to be substantially free of pin holes, but too thick to allow the formation of patterns as finely detailed as in a 500 nanometer thick layer. In addition, to avoid the position correspondence of mask defect induced pin holes which might appear in even 2000 nanometer photoresist, the second layer is exposed to an actinic radiation pattern using a different mask, with a slightly coarser pattern. Thereby, the second layer is exposed over and around the immediate region of the small, high resolution, aperture in the first layer. Upon subsequent development, the composite two-layer structure would in principle provide a high resolution aperture in the first layer communicating with a correspondingly positioned yet somewhat larger aperture in the upper layer.
In practice this approach frequently causes a loss of resolution as to small passages in the first layer because the region of the first layer defining each high resolution aperture has been exposed and developed twice. It is well-known in the art that a single exposure and development cycle tends to produce positive sloping aperture walls. Two such exposure and development cycles increase the degree of the slope in the first layer, leaving a tapered rather than vertical photoresist aperture. A tapered aperture is undesirable, particularly if the photoresist mask is to subsequently be employed to define an ion implant pattern. Thus, there remains a need for a high resolution photoresist process which provides a resist barrier which is adequately pinhole free, and which also maintains the requisite shape of the high resolution photoresist pattern resolution. A successful process would preferably also be characterized by a reduced number of handling steps as compared with the above mentioned two layer process, such as would be obtained if the process required only one development step.
Another photoresist resolution problem arises because of the multi-layered nature of present integrated circuit semiconductor devices. The surface topography of integrated circuit wafers in the latter stages of fabrication is far from planar, being characterized by a multiplicity of steps each of the general order of several hundred nanometers, such steps representing the edges of metallizations, nitride capping layers, and a variety of other layer boundaries which are inherent to the particular fabrication processes used. To achieve the resolution required for the small geometries presently sought, focus and fringing defects must be minimized by using a highly planar photoresist surface during exposure. If the photoresist layer is too thin, it will generally replicate the surface topography of the substrate. Thus, it becomes necessary in the latter stages of fabrication to employ photoresist films of substantially increased thickness to planarize the surface topography. Such "planarizing" layers are typically chosen to be two thousand to three thousand nanometers thick.
To achieve maximum pattern resolution in a barrier produced from such a thick resist layer, it is common to form a three layer masking structure, using a relatively thick photoresist layer of two microns thickness or greater, covered by multiple thin supplemental barrier layers. In practice the top layer is a thin photoresist and the next layer down is formed of an inorganic material such as silicon dioxide. By following a complex series of pattern exposures, etches, and two separate photoresist development steps, a masking structure of adequate resolution is achieved to provide the substrate etching barrier. FIGS. 4A-4C show such a conventional system, discussion of the details of which will be deferred to the Description of the Invention. A detailed discussion of this technique appears in the article "Multilayer Resists for Fine Line Optical Lithography" by Ong et al., Solid State Technology, p. 155 (June 1984).
The above mentioned processes are not only quite complex but they inherently require multiple manual handling operations involving additional costs and likelihood of damage. Wafer damage occurring in the latter stages of processing is a significant concern, since the individual wafers have become quite valuable by this point.